Z2RAM: Georgia Tech’s New Memory Chip Could Transform AI

A new memory technology emerging from Georgia Tech has attracted attention from one of the semiconductor industry’s most recognisable executives. Pat Gelsinger, former CEO of Intel and now a general partner at investment firm Playground Global, believes the technology developed by Nagare Labs could represent an important breakthrough in computer memory after decades of limited innovation in widely deployed memory architectures.

The technology is called Z2RAM. Developed by researchers associated with the Georgia Institute of Technology, it aims to combine the high speed of Static Random Access Memory (SRAM) with the greater storage density of Dynamic Random Access Memory (DRAM).

The idea addresses a growing problem in Artificial Intelligence infrastructure. Modern AI accelerators can perform enormous numbers of calculations, but their performance is increasingly constrained by how quickly data can move between processors and memory. This limitation is commonly known as the memory wall.

Nagare Labs believes its new architecture could help reduce that bottleneck by placing high-capacity, high-speed memory closer to computing logic. The company has raised $5 million in seed funding led by Playground Global to advance the technology from laboratory research towards commercial development.

What Is Nagare Labs?

Nagare Labs is a semiconductor startup spun out of research conducted at the Georgia Institute of Technology. It was founded by professors and semiconductor researchers Suman Datta and Shimeng Yu, who have spent years investigating next-generation memory technologies.

The company’s work builds on research involving oxide semiconductors, transistor-based memory cells and advanced memory architectures. Its objective is to develop a new memory tier that can offer high performance and storage density while remaining compatible with practical semiconductor manufacturing processes.

Both founders bring experience in semiconductor research. Suman Datta has worked on advanced transistor technologies, including high-k metal-gate and Tri-Gate architectures. Shimeng Yu has conducted research into emerging memory technologies and developed NeuroSim, an open-source simulator used to explore emerging memory and AI hardware designs.

Nagare Labs is attempting to turn this academic research into a commercially viable product. Its main technology, Z2RAM, is designed to address limitations in existing memory systems used by processors and AI accelerators.

What Is Z2RAM and How Does It Work?

Z2RAM is a transistor-based, capacitorless memory architecture. Its name reflects its two-transistor design, which uses the electrical characteristics of transistors to store and access information rather than relying on the conventional capacitor-based structure found in DRAM.

To understand why this matters, it is useful to look at how the two major types of high-speed computer memory work.

SRAM: Extremely Fast but Expensive in Space

SRAM is widely used for processor caches because it offers very fast access to stored information. It does not require the periodic refreshing associated with conventional DRAM, making it suitable for applications where processors need frequent access to small amounts of data.

However, SRAM cells require multiple transistors, making them relatively large compared with DRAM cells. This limits how much SRAM can be placed on a processor die without consuming expensive silicon area.

For AI accelerators, the limitation is particularly important because large models and complex workloads need access to enormous quantities of data. Increasing SRAM capacity can improve performance, but it also increases chip area and manufacturing costs.

DRAM: Higher Density but Different Performance Trade-offs

DRAM stores information using electrical charge in capacitors. Its comparatively compact cell design makes it possible to provide much greater storage capacity at a lower cost per bit than SRAM.

However, DRAM cells require periodic refreshing because their stored charge gradually leaks away. Reading information from a conventional DRAM cell is also destructive, meaning the data must be restored after the read operation.

Although DRAM provides the capacity needed for large computing workloads, it generally cannot match SRAM’s access speed and latency characteristics.

Z2RAM Attempts to Combine the Advantages

Nagare Labs wants to reduce the gap between these technologies. Z2RAM uses two transistors rather than the conventional transistor-and-capacitor arrangement found in DRAM.

One transistor is used to write information, while the gate capacitance of another transistor acts as the charge-storage mechanism. A separate read operation can sense the stored information without draining the charge in the same way as a conventional DRAM read.

This non-destructive reading approach could reduce the need for the write-back operation associated with conventional DRAM access.

The architecture is designed to deliver SRAM-like speed while achieving much greater bit density. Nagare also intends to build the memory in vertically stacked layers, allowing more storage capacity to be placed close to computing logic.

The company’s longer-term manufacturing concept draws inspiration from the layered production approach used in NAND flash memory. If successfully implemented, this could allow memory capacity to increase without requiring the same amount of additional silicon area used by conventional SRAM.

What Makes Z2RAM Different From Existing Memory Technologies?

The main distinction is its attempt to combine three characteristics that are difficult to achieve together: high speed, high storage density and scalable manufacturing.

According to the company’s projections, its first-generation Z2RAM could offer around five times the density of SRAM, speeds up to 14 times faster than DRAM and approximately three times lower read energy than SRAM.

These figures represent projected performance targets rather than results from a commercially available memory product. They should not be confused with independently demonstrated performance across a production-ready chip.

The research behind the technology has nevertheless produced encouraging experimental results. Work by the founders and their research groups has demonstrated improvements in charge retention, including a three-transistor experimental cell that retained data for more than 300 seconds at 85 degrees Celsius under the reported test conditions.

That result is important because heat and charge leakage are major challenges for compact memory cells. However, laboratory measurements of individual experimental cells do not establish that a complete Z2RAM product can meet commercial requirements for speed, reliability, density and manufacturing yield.

The distinction between demonstrated research results and projected commercial performance will be important as Nagare moves towards developing larger memory arrays.

Why Could Z2RAM Be Important for the AI Industry?

Artificial intelligence models require enormous amounts of data to be stored, retrieved and processed. Training and running large models involve moving information between memory and computing units continuously.

Even when a processor has substantial computational capability, it cannot operate at its full potential if data arrives too slowly. This is one reason memory bandwidth and capacity have become major considerations in the design of modern AI hardware.

Addressing the AI Memory Wall

The memory wall describes the growing gap between improvements in processor performance and the speed at which memory systems can supply data.

In AI workloads, this problem can lead to expensive processors waiting for information instead of performing calculations. As models become larger and more complex, the amount of data that must move through the system increases.

Nagare’s Z2RAM is designed to reduce this problem by providing more memory capacity close to the computing logic. If successful, it could help processors access larger amounts of data without relying entirely on conventional cache and external memory arrangements.

Reducing Dependence on Expensive SRAM

SRAM provides excellent performance, but expanding its capacity can consume a substantial amount of processor silicon. This makes large on-chip caches expensive and difficult to scale.

Nagare’s projected fivefold improvement in bit density could allow chip designers to fit considerably more memory into a similar area. For example, a memory tile that could hold 64MB using a particular SRAM design might theoretically accommodate around 320MB using a technology delivering five times the density.

Such an increase could be valuable for AI accelerators that depend on fast access to frequently used model data. It could also reduce the need to distribute certain workloads across as many separate processors, although the actual benefits would depend on the final architecture and application.

Improving Energy Efficiency

Moving data between processors and external memory consumes energy. In large AI data centres, this can become a significant part of the overall computing cost.

By placing additional memory closer to the processor and reducing the distance data must travel, Z2RAM could potentially lower some communication-related energy costs.

Nagare’s projected lower read-energy requirements could provide another advantage if confirmed in complete memory systems. Lower energy consumption would be particularly valuable for data centres operating large numbers of AI accelerators around the clock.

Supporting More Efficient AI Inference

AI inference involves using trained models to generate responses, analyse information or perform other tasks. Large language models often need to retrieve substantial amounts of information while generating outputs.

Memory capacity and bandwidth can influence how efficiently these systems serve multiple users and handle large workloads.

If Z2RAM delivers its intended combination of density and speed, it could help AI hardware manufacturers build systems capable of handling more data closer to computing units. That could improve efficiency and potentially reduce some infrastructure costs.

However, Z2RAM would not independently make AI models faster or eliminate the need for existing memory technologies. Its impact would depend on how successfully chip designers integrate it into complete computing systems.

Why Pat Gelsinger Believes the Technology Matters

Pat Gelsinger has argued that the semiconductor industry has seen limited innovation in the major memory types used at scale over the past three decades. SRAM, DRAM and flash memory remain the dominant technologies across a wide range of computing products.

He sees Z2RAM as a possible opportunity to introduce a new memory architecture at a time when AI workloads are creating unprecedented demand for storage capacity and bandwidth.

Gelsinger has joined Nagare Labs’ board and is associated with Playground Global, the investment firm that led the company’s first funding round.

His interest reflects a broader industry concern: improvements in AI computing are increasingly dependent not only on faster processors but also on better ways of storing and moving information.

However, backing from an experienced semiconductor executive does not guarantee that a new memory technology will succeed. The history of the industry includes several promising memory designs that struggled to achieve commercial adoption because of manufacturing, reliability and integration challenges.

How Much Money Has Nagare Labs Raised?

Nagare Labs raised $5 million in seed funding, with Playground Global leading the investment round announced in October 2026.

The funding is intended to support the company’s development of Z2RAM and help move its research beyond laboratory prototypes. For a semiconductor startup, the investment represents an initial step towards the substantial engineering and manufacturing work required to produce a commercial memory product.

The company will need to develop larger working memory arrays, improve reliability, establish manufacturing partnerships and demonstrate that its technology can be integrated into real computing systems.

Although $5 million provides an initial financial foundation, scaling a new semiconductor technology can require considerably more capital, specialist equipment and cooperation with established chip manufacturers.

What Challenges Must Z2RAM Overcome Before Commercialisation?

Despite its potential, Z2RAM remains at an early stage of development. Its laboratory results and performance projections are promising, but several challenges must be addressed before it can become a widely used memory technology.

Manufacturing at Commercial Scale

Nagare needs access to semiconductor fabrication facilities capable of producing larger memory structures. The company has been looking for a research and development fabrication partner to move beyond the university clean-room environment.

Producing a small experimental memory cell is very different from manufacturing millions or billions of reliable cells on commercial chips. The technology must demonstrate consistent performance across large arrays and acceptable manufacturing yields.

Reliability and Data Retention

One of the major technical challenges is ensuring that stored information remains reliable under different operating temperatures and electrical conditions.

Because Z2RAM relies on charge storage in transistor structures, small changes in transistor characteristics can affect the stored information. The research team must continue improving cell design and validating performance across a wider range of operating conditions.

Long-term reliability testing will be essential before manufacturers can consider using the technology in expensive AI accelerators and data-centre hardware.

Integration With AI Processors

Another challenge is integrating Z2RAM with existing processor architectures. The technology is intended to sit close to computing logic, potentially using advanced three-dimensional integration methods.

However, there is currently no widely established industry standard for connecting this new type of memory to AI accelerators. Nagare may need to work with chipmakers to develop suitable interfaces and packaging arrangements.

Without reliable integration methods, even a high-performance memory cell could struggle to gain adoption in commercial products.

Competition From Established Memory Technologies

Z2RAM will also face competition from established memory manufacturers and other emerging technologies. High-bandwidth memory, advanced DRAM, SRAM stacking and other approaches are already being developed to address AI hardware requirements.

Chipmakers will need clear evidence that Z2RAM offers meaningful advantages in cost, performance, energy efficiency and reliability before replacing or supplementing existing solutions.

When Could Z2RAM Reach the Market?

Nagare Labs has outlined a long development path for its technology. The company is targeting working Z2RAM memory tile samples within approximately four years, while production shipments could take until the next decade if development proceeds successfully.

These are company development goals, not confirmed commercial launch dates. Achieving them will depend on progress in fabrication, cell reliability, packaging and partnerships with chip manufacturers.

The company has indicated that it is open to collaborating directly with semiconductor companies to integrate its memory into their designs. Such partnerships could become important because commercialising a new memory architecture requires expertise and resources beyond the capabilities of a small research-led startup.

Could Z2RAM Become the Next Major Memory Breakthrough?

Z2RAM addresses one of the most important challenges facing modern AI infrastructure: the difficulty of combining high memory capacity with fast data access and efficient energy use.

Its transistor-based, capacitorless design offers a different approach to the limitations of conventional SRAM and DRAM. The possibility of stacking memory layers directly alongside computing logic could also create new opportunities for AI accelerator design.

Pat Gelsinger’s involvement and Playground Global’s $5 million investment have brought significant attention to the project. The research emerging from Georgia Tech also provides a technical foundation for further development.

Nevertheless, the technology is not yet a commercially available replacement for existing memory products. Its projected performance must be demonstrated in complete devices, and the company still needs to overcome manufacturing, reliability and integration challenges.

If Nagare Labs can turn its laboratory research into reliable, affordable and scalable memory chips, Z2RAM could become an important addition to the semiconductor industry’s AI hardware ecosystem. For now, it is a promising early-stage technology rather than a proven revolution, but its development highlights how the next phase of AI progress may depend as much on memory innovation as on faster processors.